ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.346 VORR (immediate)
This instruction takes the contents of the destination vector, performs a bitwise OR with an immediate
constant, and returns the result into the destination vector. For the range of constants available, see One
register and a modified immediate value on page A7-21.
Encoding T1 / A1 Advanced SIMD
VORR. , #
VORR. , #
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 i 1 1 1 1 1 D 0 0 0 imm3 Vd cmode 0 Q 0 1 imm4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode 0 Q 0 1 imm4
if cmode == ‘0’ || cmode == ‘11’ then SEE VMOV (immediate);
if Q == ‘1’ && Vd == ‘1’ then UNDEFINED;
imm64 = AdvSIMDExpandImm(‘0’, cmode, i:imm3:imm4);
d = UInt(D:Vd); regs = if Q == ‘0’ then 1 else 2;
A8-678 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B