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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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<strong>ARM</strong>v6 Differences<br />

For <strong>ARM</strong>v6, TLB lockdown must comply with one of the lockdown models described in c10, VMSA TLB<br />

lockdown support on page AppxH-59.<br />

G.7.19 c11, DMA support<br />

The <strong>ARM</strong>v6 DMA support for TCMs described in The <strong>ARM</strong> <strong>Architecture</strong> <strong>Reference</strong> <strong>Manual</strong> (DDI 0100) is<br />

considered IMPLEMENTATION DEFINED <strong>and</strong> not included in this manual. <strong>ARM</strong>v6 is therefore the same as<br />

<strong>ARM</strong>v7. See CP15 c11, Reserved for TCM DMA registers on page B3-147.<br />

G.7.20 c12, VMSA support for the Security Extensions<br />

CP15 c12 support for the Security Extensions in <strong>ARM</strong>v6 is the same as in <strong>ARM</strong>v7:<br />

the Vector Base Address Register, VBAR<br />

the Monitor Base Address Register, MVBAR<br />

the Interrupt Status Register, ISR.<br />

For details see CP15 c12, Security Extensions registers on page B3-148.<br />

G.7.21 c13, Context ID support<br />

Both PMSAv6 <strong>and</strong> VMSAv6 require the CONTEXTIDR described in:<br />

c13, Context ID Register (CONTEXTIDR) on page B3-153, for a VMSA implementation<br />

c13, Context ID Register (CONTEXTIDR) on page B4-76, for a PMSA implementation.<br />

In addition:<br />

A VMSAv6 implementation requires the FCSEIDR, described in c13, FCSE Process ID Register<br />

(FCSEIDR) on page B3-152. In <strong>ARM</strong>v6 the FCSE must be implemented. For more information, see<br />

Appendix E Fast Context Switch Extension (FCSE).<br />

An <strong>ARM</strong>v6K implementation requires the Software Thread ID registers described in CP15 c13<br />

Software Thread ID registers on page B3-154.<br />

Note<br />

In <strong>ARM</strong>v6, after any change to the CONTEXTIDR or FCSEIDR, software must use the CP15 branch<br />

predictor maintenance operations to flush the virtual addresses affected by the change. If the branch<br />

predictor is not invalidated in this way, attempting to execute an old branch might cause UNPREDICTABLE<br />

behavior. <strong>ARM</strong>v7 does not require branch predictors to be invalidated after a change to the CONTEXTIDR<br />

or FCSEIDR.<br />

G.7.22 c15, IMPLEMENTATION DEFINED<br />

As in <strong>ARM</strong>v7, CP15 c15 is reserved for IMPLEMENTATION DEFINED use. Typically, it is used for<br />

processor-specific runtime <strong>and</strong> test features.<br />

AppxG-54 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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