ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
B4.6.25 CP15 c7, Cache maintenance and other functions
The CP15 c7 registers are used for cache maintenance operations, and also provide barrier operations.
Figure B4-8 shows the CP15 c7 registers.
CRn opc1 CRm opc2
c7 0 c0 4
NOP
c1 {0,6} Cache maintenance operations ‡
c5 {0,1} Cache maintenance operations
4
CP15ISB, Instruction Synchronization Barrier operation
{6,7} Branch predictor maintenance operations
c6 {1,2} Cache maintenance operations
c10 {1,2} Cache maintenance operations
{4,5} Data barrier operations
c11
1
DCCMVAU, cache maintenance operation
c13 1 NOP
c14 {1,2} Cache maintenance operations
Read-only Read/Write
Write-only Bold text = Accessible in User mode
‡ Part of the Multiprocessing Extensions
Figure B4-8 CP15 c7 registers in a PMSA implementation
All CP15 c7 encodings not shown in Figure B4-8 are UNPREDICTABLE, see Unallocated CP15 encodings on
page B4-27.
The CP15 c7 operations are described in:
CP15 c7, Cache and branch predictor maintenance functions
CP15 c7, Miscellaneous functions on page B4-72.
B4.6.26 CP15 c7, Cache and branch predictor maintenance functions
CP15 c7 provides a number of functions. This section describes only the CP15 c7 cache and branch
predictor maintenance operations. Branch predictor operations are included in this section, because they
operate in a similar way to the cache maintenance operations.
Note
ARMv7 introduces significant changes in the CP15 c7 operations. Most of these changes are because, from
ARMv7, the architecture covers multiple levels of cache. This section only describes the ARMv7
requirements for these operations. For details of these operations in previous versions of the architecture see:
c7, Cache operations on page AppxG-38 for ARMv6
c7, Cache operations on page AppxH-49 for ARMv4 and ARMv5.
B4-68 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B