ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
B3.6 Memory access control
Access to a memory region is controlled by the access permission bits and the domain field in the TLB entry.
These form part of the translation table entry formats described in Translation tables on page B3-7. The bits
and fields are summarized in First-level descriptors on page B3-8 and Second-level descriptors on
page B3-10.
The TLB memory access controls are described in:
Access permissions
The Execute Never (XN) attribute and instruction prefetching on page B3-30
Domains on page B3-31.
B3.6.1 Access permissions
The access permission bits control access to the corresponding memory region. If an access is made to an
area of memory without the required permissions, a Permission fault is generated if the domain is set to
Client. The access permissions are determined by the AP[2:0] bits in the translation table entry. The XN bit
in the translation table entry provides an additional permission bit for instruction fetches.
AP[2] AP[1:0]
Note
Before VMSAv7, the SCTLR.S and SCTLR.R bits also affect the access permissions. For more
information, see Translation attributes on page AppxH-22.
From VMSAv7, the full set of access permissions shown in Table B3-4 are only supported when the
SCTLR.AFE bit is set to 0. When SCTLR.AFE = 1, the only supported access permissions are those
described in Simplified access permissions model on page B3-29.
In previous issues of the ARM Architecture Reference Manual and in some other documentation, the
AP[2] bit in the translation table entries is described as the APX bit.
Table B3-4 shows the encoding of the access permissions:
Privileged
permissions
User
permissions
Table B3-4 VMSAv7 MMU access permissions
Description
0 00 No access No access All accesses generate Permission faults
0 01 Read/write No access Privileged access only
0 10 Read/write Read-only Writes in User mode generate Permission faults
0 11 Read/write Read/write Full access
1 00 - - Reserved
B3-28 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B