ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Bit [23] RAO/SBOP.
Virtual Memory System Architecture (VMSA)
When the Security Extensions are implemented, this bit is banked between the Secure and
Non-secure versions of the register.
For more information, see Vectored interrupt support on page B1-32.
If the implementation does not support IMPLEMENTATION DEFINED FIQ and IRQ vectors
then this bit is RAZ/WI.
U, bit [22] In ARMv7 this bit is RAO/SBOP, indicating use of the alignment model described in
Alignment support on page A3-4.
For details of this bit in earlier versions of the architecture see Alignment on page AppxG-6.
FI, bit [21] Fast Interrupts configuration enable bit. This bit can be used to reduce interrupt latency in
an implementation by disabling IMPLEMENTATION DEFINED performance features. The
permitted values of this bit are:
0 All performance features enabled.
1 Low interrupt latency configuration. Some performance features disabled.
When the Security Extensions are implemented, this bit is common to the Secure and
Non-secure versions of the register.
This bit is:
a read/write bit if the Security Extensions are not implemented
if the Security Extensions are implemented:
— a read/write bit if the processor is in Secure state
— a read-only bit if the processor is in Non-secure state.
For more information, see Low interrupt latency configuration on page B1-43.
If the implementation does not support a mechanism for selecting a low interrupt latency
configuration this bit is RAZ/WI.
Bit [20:19] RAZ/SBZP.
Bit [18] RAO/SBOP.
HA, bit [17] Hardware Access Flag Enable bit. If the implementation provides hardware management of
the access flag this bit enables the access flag management:
0 Hardware management of access flag disabled
1 Hardware management of access flag enabled.
If the Security Extensions are implemented then this bit is banked between the Secure and
Non-secure versions of the register.
If the implementation does not provide hardware management of the access flag then this
bit is RAZ/WI.
For more information, see Hardware management of the access flag on page B3-21.
Bit [16] RAO/SBOP.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-99