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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Virtual Memory System <strong>Architecture</strong> (VMSA)<br />

The following subsections give more information about UNPREDICTABLE <strong>and</strong> UNDEFINED behavior for<br />

CP15:<br />

Unallocated CP15 encodings<br />

Rules for MCR <strong>and</strong> MRC accesses to CP15 registers<br />

Effects of the Security Extensions on page B3-70.<br />

Unallocated CP15 encodings<br />

When MCR <strong>and</strong> MRC instructions perform CP15 operations, the CRn value for the instruction is the major<br />

register specifier for the CP15 space. Accesses to unallocated major registers are UNDEFINED. For the<br />

<strong>ARM</strong>v7-A <strong>Architecture</strong>, this means that:<br />

for an implementation that includes the Security Extensions, accesses with = {c4, c14} are<br />

UNDEFINED<br />

for an implementation that does not include the Security Extensions, accesses with<br />

= {c4, c12, c14} are UNDEFINED<br />

In an allocated CP15 major register specifier, MCR <strong>and</strong> MRC accesses to all unallocated encodings are<br />

UNPREDICTABLE for privileged accesses. For the <strong>ARM</strong>v7-A architecture this means that:<br />

if the Security Extensions are implemented, any privileged MCR or MRC access with != {c4, c14}<br />

<strong>and</strong> a combination of , <strong>and</strong> values not shown in Figure B3-10 on page B3-65 is<br />

UNPREDICTABLE.<br />

if the Security Extensions are not implemented, any privileged MCR or MRC access with<br />

!= {c4, c12, c14} <strong>and</strong> a combination of , <strong>and</strong> values not shown in<br />

Figure B3-10 on page B3-65 is UNPREDICTABLE.<br />

Note<br />

As shown in Figure B3-10 on page B3-65, accesses to unallocated principal ID registers map onto MIDR.<br />

These are accesses with = c0, =0, = c0, <strong>and</strong> = {4, 6, 7}.<br />

Rules for MCR <strong>and</strong> MRC accesses to CP15 registers<br />

All MCR operations from the PC are UNPREDICTABLE for all coprocessors, including for CP15.<br />

All MRC operations to APSR_nzcv are UNPREDICTABLE for CP15.<br />

The following accesses are UNPREDICTABLE:<br />

an MCR access to an encoding for which no write behavior is defined in any circumstances<br />

an MRC access to an encoding for which no read behavior is defined in any circumstances.<br />

Except for CP15 encoding that are accessible in User mode, all MCR <strong>and</strong> MRC accesses from User mode are<br />

UNDEFINED. This applies to all User mode accesses to unallocated CP15 encodings. Individual register<br />

descriptions, <strong>and</strong> the summaries of the CP15 major registers, show the CP15 encodings that are accessible<br />

in User mode.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. B3-69

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