ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
Note
System level register names, such as R0_usr, R8_usr, and R8_fiq, are used when it is necessary to
identify a specific register. The Application level names refer to the registers for the current mode,
and usually are sufficient to identify a register.
In ARMv7, the Security Extensions can be implemented only as part of an ARMv7-A
implementation.
Each of the exception modes selects a different copy of the banked SP and LR, because these registers have
special functions on exception entry:
SP This enables the exception handler to use a different stack to the one in use when the
exception occurred. For example, it can use a stack in privileged memory rather than one in
unprivileged memory.
LR The exception return address is placed in the banked LR of the exception mode. This means
the use of the LR by the application is not corrupted. The address placed in the banked LR
is at an exception-dependent offset from the next instruction to be executed in the code in
which the exception occurred. This address enables the exception handler to return to that
code, so the processor can resume execution of the code. Table B1-4 on page B1-34 shows
the LR value saved on entry to each of the exception modes.
In addition:
FIQ mode provides its own mappings for the general-purpose registers R8 to R12. These enable very
fast processing of interrupts that are simple enough to be processed using only registers R8 to R12,
SP, LR, and PC, without affecting the corresponding registers of the mode in which the interrupt was
taken.
In an exception mode the processor can access the SPSR for that mode. There is no SPSR for User
mode and System mode.
In all ARMv7-A and ARMv7-R implementations:
Every mode except User mode is privileged.
User mode and System mode share the same register file. The only difference between System and
User modes is that System mode runs with privileged access.
For more information about the application level view of the SP, LR, and the Program Counter (PC), and
the alternative descriptions of them as R13, R14 and R15, see ARM core registers on page A2-11.
B1-10 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B