ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
Table C10-16 Vector catch operation, when Security Extensions are implemented (continued)
DBGVCR bit Vector catch enable Security state
Secure state vector catches on exception mode vectors
[7] FIQ VE = 0 Secure VBARS + 0x0000001C 0xFFFF001C
VE = 1 Secure Most recent Secure FIQ address a
[6] IRQ VE = 0 Secure VBARS + 0x00000018 0xFFFF0018
VE = 1 Secure Most recent Secure IRQ address a
[4] Data Abort Secure VBARS + 0x00000010 0xFFFF0010
[3] Prefetch Abort Secure VBARS + 0x0000000C 0xFFFF000C
[2] SVC Secure VBARS + 0x00000008 0xFFFF0008
[1] Undefined Instruction Secure VBARS + 0x00000004 0xFFFF0004
Reset vector catch b
[0] Reset b 0x00000000 0xFFFF0000
a. For more information see Vector catch debug events and vectored interrupt support on page C3-22.
b. The value of the Reset vector is always independent of the Vector Base Address Register values. The security state
dependence of Reset vector catches depends on the Debug architecture version. In v7 Debug, Reset vector catches
are generated regardless of the security state of the processor. In v6 Debug and v6.1 Debug, Reset vector catches
are generated only in Secure state.
In a v6.1 Debug implementation on a processor that implements the Security Extensions but does not
implement DBGVCR bits [31, 30, 28:25, 15:14, 12:10]:
in Non-secure state, bits [7:6, 4:1] apply to offsets from VBARNS.
Configured exception vectors
Normal (V == 0) High (V == 1)
in Secure state, bits [7:6, 4:1] apply to offsets from VBARS and bits [7:6, 4:2] also apply to offsets
from MVBAR.
C10-74 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B