ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Common Memory System Architecture Features
The ARMv7 specification of the cache maintenance operation describe what they are guaranteed to do in a
system. It does not limit other behaviors that might occur, provided they are consistent with the requirements
for cache behavior described in Cache behavior on page B2-5.
This means that as a side-effect of a cache maintenance operation:
any location in the cache might be cleaned
any unlocked location in the cache might be cleaned and invalidated.
Note
ARM recommends that, for best performance, such side-effects are kept to a minimum. In particular, when
the Security Extensions are implemented ARM strongly recommends that the side-effects of operations
performed in Non-secure state do not have a significant performance impact on execution in Secure state.
Effect of the Security Extensions on the cache maintenance operations
When the Security Extensions are implemented, each security state has its own physical address space. For
details of how this affects the cache maintenance operations see The effect of the Security Extensions on the
cache operations on page B3-27.
The ARMv7 abstraction of the cache hierarchy
The following subsections describe the ARMv7 abstraction of the cache hierarchy:
Cache hierarchy abstraction for address-based operations
Cache hierarchy abstraction for set/way-based operations on page B2-16.
Example code for cache maintenance operations on page B2-16 gives an example of cache maintenance
code, that can be adapted for other cache operations, and Boundary conditions for cache maintenance
operations on page B2-17 gives more information about the cache operations.
Cache hierarchy abstraction for address-based operations
The addressed-based cache operations are described as operating by MVA. Each of these operations is
always qualified as being one of:
performed to the point of coherency
performed to the point of unification.
See Terms used in describing cache operations on page B2-10 for definitions of point of coherency and
point of unification, and more information about possible meanings of MVA.
This means that the full list of possible address-based cache operations is:
Invalidate data cache or unified cache line by MVA to the point of coherency
Clean data cache or unified cache line by MVA to the point of coherency
Clean data cache or unified cache line by MVA to the point of unification
Clean and invalidate data cache or unified cache line by MVA to the point of coherency
Invalidate instruction cache line by MVA to the point of unification.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B2-15