ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The CPUID Identification Scheme
SynchPrim_instrs, bits [15:12]
SVC_instrs, bits [11:8]
SIMD_instrs, bits [7:4]
This field is used with the SynchPrim_instrs_frac field of ID_ISAR4 to indicate the
supported Synchronization Primitive instructions. Table B5-2 shows the permitted values of
these fields:
All combinations of SynchPrim_instrs and SynchPrim_instrs_frac not shown in Table B5-2
are reserved.
Indicates the supported SVC instructions. Permitted values are:
0b0000 Not supported.
0b0001 Adds support for the SVC instruction.
Note
Table B5-2 Synchronization Primitives support
SynchPrim_instrs SynchPrim_instrs_frac Supported Synchronization Primitives
0000 0000 None supported
0001 0000 Adds support for the LDREX and STREX instructions.
0001 0011 As for [0001,0000], and adds support for the CLREX, LDREXB,
LDREXH, STREXB, and STREXH instructions.
0010 0000 As for [0001,0011], and adds support for the LDREXD and
STREXD instructions.
The SVC instruction was called the SWI instruction in previous versions of the ARM
architecture.
Indicates the supported SIMD instructions. Permitted values are:
0b0000 None supported.
0b0001 Adds support for the SSAT and USAT instructions, and for the Q bit in the PSRs.
0b0011 As for 0b0001, and adds support for the PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16,
QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8,
SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16,
UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8,
UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, and UXTB16
instructions.
Also adds support for the GE[3:0] bits in the PSRs.
B5-30 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B