ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
It is IMPLEMENTATION DEFINED whether the DBGDSMCR is included in a v6 Debug or v6.1 Debug
implementation.
The format of the DBGDSMCR is:
31 4
Reserved, UNK/SBZP
Bits [31:4] Reserved, UNK/SBZP.
TLB matching bits, bits [3:2]
Instruction TLB matching, nIUM
Data TLB matching, nDUM
Instruction TLB loading, nIUL
Data TLB loading, nDUL
Either or both of these bits might not be implemented, in which case the bit is RAZ/WI. If
implemented these bits are:
nIUM, bit [3] Instruction TLB matching bit, where separate Data and Instruction
TLBs are implemented.
nDUM, bit [2] Data or Unified TLB matching bit.
The possible values of an implemented TLB matching bit are:
0 Request disabling of TLB matching for memory operations issued by a
debugger when the processor is in Debug state
1 Normal operation of TLB matching for memory operations issued by a
debugger when the processor is in Debug state.
When TLB matching is disabled, all memory accesses normally checked against a TLB are
not checked against the TLB. For every access the next level of translation is performed. The
results are not cached in the TLB, and no TLB entries are evicted. The next level of
translation is used for every access.
The next level of translation might mean looking in the next level TLB, or doing a
translation table walk, depending on the numbers of levels of TLB implemented.
Note
If TLB matching is disabled, and TLB maintenance functions have not been correctly
performed by the system being debugged, for example, if the TLB has not been flushed
following a change to the translation tables, memory accesses made by the debugger might
not undergo the same virtual to physical memory mappings as the application being
debugged.
A debugger can create temporary alternative memory mappings by altering the contents of
the external translation tables and disabling all levels of TLB matching. However, for
normal debugging operations, ARM recommends that the TLB Matching bit is set to 1.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-85
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