ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

B3.2.3 Enabling and disabling the MMU
Virtual Memory System Architecture (VMSA)
The MMU can be enabled and disabled by writing to the SCTLR.M bit, see c1, System Control Register
(SCTLR) on page B3-96. On reset, this bit is cleared to 0, disabling the MMU.
When the MMU is disabled, memory accesses are treated as follows:
All data accesses are treated as Non-cacheable and Strongly-ordered. Unexpected data cache hit
behavior is IMPLEMENTATION DEFINED.
The treatment of instruction accesses depends on the value of the SCTLR.I bit:
When I == 0
All instruction accesses are Non-cacheable.
When I == 1
All instruction accesses are Cacheable:
Inner Write-Through no Write-Allocate
Outer Write-Through no Write-Allocate.
In both cases all instruction accesses are Non-shareable, Normal memory.
Note
On some implementations, if the SCTLR.TRE bit is set to 0 then this behavior can be changed by the
remap settings in the memory remap registers, see CP15 c10, Memory Remap Registers on
page B3-143. The details of TEX remapping when SCTLR.TRE is set to 0 are IMPLEMENTATION
DEFINED, see SCTLR.TRE, SCTLR.M, and the effect of the MMU remap registers on page B3-38.
No memory access permission checks are performed, and no aborts are generated by the MMU.
For every access the PA is equal to the MVA. This is known as a flat address mapping.
If the FCSE is implemented, the FCSE PID is SBZ when the MMU is disabled. This is the reset value
for the FCSE PID. Behavior is UNPREDICTABLE if the FCSE PID is not zero when the MMU is
disabled.
When the FCSE is implemented software must clear the FCSE PID before disabling the MMU.
CP15 cache maintenance operations act on the target cache whether the MMU is enabled or not, and
regardless of the values of the memory attributes. However, if the MMU is disabled, they use the flat
address mapping, and all mappings are considered global.
CP15 TLB invalidate operations act on the target TLB whether the MMU is enabled or not.
All relevant CP15 registers must be programmed before the MMU is enabled. This includes setting up
suitable translation tables in memory.
When the MMU is disabled, an instruction can be fetched if one of the following conditions is met:
The instruction is in the same 4KB block of memory (aligned to 4KB) as an instruction that is
required by a simple sequential execution of the program, or is in the 4KB block of memory
immediately following such a block.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-5