ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
Bits [30:N] RAZ/WI.
Px, bit [x], for x = 0 to (N-1)
Event counter x, PMNx, disable bit.
Table C10-26 shows the behavior of this bit on reads and writes.
The contents of the PMCNTENCLR Register are UNKNOWN on a core logic reset.
Note
Table C10-26 Read and write bit values for the PMCNTENCLR Register
The PMCR.E Enable bit can be used to override the settings in this register and disable all counters including
PMCCNTR, see c9, Performance Monitor Control Register (PMCR) on page C10-105. The counter enable
register retains its value when the Enable bit is 0, even though its settings are ignored.
C10.9.4 c9, Overflow Flag Status Register (PMOVSR)
The Overflow Flag Status Register, PMOVSR, holds the state of the overflow flags for:
the Cycle Count Register, PMCCNTR
each of the implemented event counters, PMNx.
To clear those flags you must write to the PMOVSR.
Value Meaning on read Action on write
0 Counter disabled No action, write is ignored
1 Counter enabled Disable counter
The PMOVSR is:
a 32-bit read/write CP15 register:
— reading the register shows the state of the overflow flags
— writing a 1 to a bit of the register clears the corresponding flag
— writing a 0 to a bit of the register has no effect
accessible in:
— privileged modes
— User mode only when the PMUSERENR.EN bit is set to 1
when the Security Extensions are implemented, a Common register
accessed using an MRC or MCR command with set to c9, set to 0, set to c12, and
set to 3.
C10-110 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B