ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Note
Common Memory System Architecture Features
In ARMv6, the SCTLR I, C, and W bits provide separate enables for the level 1 instruction cache (if
implemented), the level 1 data or unified cache, and write buffering. For more information, see c1, System
Control Register (SCTLR) on page AppxG-34.
When a cache is disabled:
it is IMPLEMENTATION DEFINED whether a cache hit occurs if a location that is held in the cache is
accessed
any location that is not held in the cache is not brought into the cache as a result of a memory access.
The SCTLR.C and SCTLR.I bits describe the enabling of the caches, and do not affect the memory attributes
generated by an enabled MMU or MPU.
If the MMU or MPU is disabled, the effects of the SCTLR.C and SCTLR.I bits on the memory attributes
are described in:
Enabling and disabling the MMU on page B3-5 for the MMU
Behavior when the MPU is disabled on page B4-5 for the MPU.
B2.2.4 Cache maintenance functionality
ARMv7 redefines the required CP15 cache maintenance operations. The two main features of this change
are:
improved support for multiple levels of cache, including abstracting how many levels of cache are
implemented.
reducing the architecturally-defined set of operations to the minimum set required for operating
systems
This section only describes cache maintenance for ARMv7. For details of cache maintenance in previous
versions of the ARM architecture see:
c7, Cache operations on page AppxG-38 for ARMv6
c7, Cache operations on page AppxH-49 for the ARMv4 and ARMv5 architectures.
Terms used in describing cache operations on page B2-10 describes the terms used in this section. Then the
following subsections describe the ARMv7 cache maintenance functionality:
ARMv7 cache maintenance operations on page B2-13
The ARMv7 abstraction of the cache hierarchy on page B2-15.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B2-9