ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Cache behavior at reset
ARMv6 Differences
In ARMv6, all cache lines in a cache, and all cached entries associated with branch prediction support, are
invalidated by a reset. This is different to the ARMv7 behavior described in Behavior of the caches at reset
on page B2-6.
G.6.3 Tightly Coupled Memory (TCM) support
Tightly Coupled Memory (TCM) support on page AppxG-9 introduced TCMs and their use at the
application level. In addition, TCMs can be used to hold critical system-level routines such as interrupt
handlers, and critical data structures such as interrupt stacks. Using TCMs can avoid indeterminate cache
accesses.
ARMv6 supports up to four banks of data TCM and up to four banks of instruction TCM. You must program
each bank to be in a different location in the physical memory map.
ARMv6 expects TCM to be used as part of the physical memory map of the system, and not to be backed
by a level of external memory with the same physical addresses. For this reason, TCM behaves differently
from a cache for regions of memory that are marked as being Write-Through Cacheable. In such regions, a
write to a memory locations in the TCM never causes an external write.
A particular memory location must be contained either in the TCM or in the cache, and cannot be in both.
In particular, no coherency mechanisms are supported between the TCM and the cache. This means that it
is important when allocating the TCM base addresses to ensure that the same address ranges are not
contained in the cache.
TCM support and VMSA
TCMs are supported in ARMv6 with VMSA support. However, there are some usage restrictions.
Restriction on translation table mappings
In a VMSA implementation, the TCM must appear to be implemented as Physically-Indexed,
Physically-Addressed memory. This means it must behave as follows:
Entries in the TCM do not have to be cleaned or invalidated by software for different virtual to
physical address mappings.
Aliases to the same physical address can exist in memory regions that are held in the TCM. This
means the translation table mapping restrictions for TCM are less restrictive than for cache memory.
See Virtual to physical translation mapping restrictions on page AppxG-26 for cache memory
restrictions.
Restriction on translation table attributes
In a VMSA implementation, the translation table entries that describe areas of memory that are handled by
the TCM can be Cacheable or Non-cacheable, but must not be marked as Shareable. If they are marked as
either Device or Strongly-ordered, or have the Shareable attribute set, the locations that are contained in the
TCM are treated as being Non-shareable, Non-cacheable.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxG-23