ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

C10.9.10 c9, User Enable Register (PMUSERENR)
Debug Registers Reference
The User Enable Register, PMUSERENR, enables or disables User mode access to the performance
monitors.
The PMUSERENR is:
a 32-bit read/write CP15 register, with access that depends on the current mode:
— in a privileged mode, the PMUSERENR is a read/write register
— in User mode, the PMUSERENR is a read-only register
when the Security Extensions are implemented, a Common register
accessed using an MRC or MCR command with set to c9, set to 0, set to c14, and
set to 0.
The format of the PMUSERENR is:
31 1 0
Reserved, UNK/SBZP
E
N
Bits [31:1] Reserved, UNK/SBZP.
EN, bit [0] User mode access enable bit. The possible values of this bit are:
0 User mode access to performance monitors disabled
1 User mode access to performance monitors enabled.
Some MCR and MRC instructions used to access the performance monitors are UNDEFINED in User mode when
User mode access to the performance monitors is disabled. For more information, see Access permissions
on page C9-12.
The PMUSERENR.EN bit is set to 0 on a core logic reset.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-117