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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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B.4 Support code requirements<br />

Common VFP Subarchitecture Specification<br />

When an instruction is bounced, control passes to the Undefined Instruction exception h<strong>and</strong>ler provided by<br />

the operating system.<br />

The operating system is expected to:<br />

1. Perform a st<strong>and</strong>ard exception entry sequence, preserving process state <strong>and</strong> re-enabling interrupts.<br />

2. Decode the bounced instruction sufficiently to determine whether it is a coprocessor instruction, <strong>and</strong><br />

if so, for which coprocessor.<br />

3. Check whether the bounced instruction is conditional, <strong>and</strong> if it is conditional, check whether the<br />

condition was passed. This ensures correct execution on implementations that perform the bounce<br />

even for an instructions that would fail its condition code check.<br />

4. Check whether the coprocessor is enabled in the access control register, <strong>and</strong> take appropriate action<br />

if not. For example, in the lazy context switch case described in Context switching with the Advanced<br />

SIMD <strong>and</strong> VFP extensions on page B1-69, the operating system context switches the VFP state.<br />

5. Call an appropriate second-level h<strong>and</strong>ler for the coprocessor, passing in:<br />

the instruction that bounced<br />

the state of the associated process.<br />

6. The second-level h<strong>and</strong>ler must indicate whether the bounced instruction is to be retried or skipped.<br />

It can also signal an additional exception that must be passed on to the application.<br />

7. Restore the original process, transferring control to an exception h<strong>and</strong>ler in the application context if<br />

necessary.<br />

If the bounced instruction is a VFP instruction, control is passed to a second-level h<strong>and</strong>ler for VFP<br />

coprocessor instructions. For the Common VFP subarchitecture this:<br />

1. Uses the FPEXC.EX <strong>and</strong> FPEXC.DEX bits to determine the bounced instruction <strong>and</strong> associated<br />

h<strong>and</strong>ling. The three possible cases are:<br />

FPEXC.EX == 0, FPEXC.DEX == 0<br />

The bounce was synchronous. The exception-generating instruction is the instruction that<br />

bounced:<br />

If the exception-generating instruction is not a CDP instruction, or the version of the<br />

subarchitecture is before version 3, the bounce was caused by an unallocated<br />

instruction encoding or a VFP access permission fault. Branch to operating system<br />

specific code that takes appropriate action.<br />

If the exception-generating instruction is a CDP instruction, check whether the<br />

bounce was caused by a VFP access permission fault:<br />

— If it is a VFP access permission fault, branch to operating system specific<br />

code that takes appropriate action.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. AppxB-11

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