ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Execute Never (XN)
ARMv6 Differences
The ARMv7 requirement that instruction prefetches are not made from read-sensitive devices also applies
to earlier versions of the architecture:
ARMv7 requires you to mark all read-sensitive devices with the Execute-never (XN) to ensure that
this requirement is met, see The Execute Never (XN) attribute and instruction prefetching on
page B3-30
before ARMv7, how this requirement is met is IMPLEMENTATION DEFINED.
Legacy translation table format
ARMv6 legacy support only includes the coarse translation table type as described in Second level Coarse
page table descriptor format on page AppxH-25. ARMv6 does not support the fine level 2 Page table
format. Therefore the legacy translation table format includes subpage access permissions but does not
support 1KB Tiny pages. Table G-4 shows the legacy first level translation table entry formats.
Table G-4 Legacy first level descriptor format
31 20 19 14 12 11 10 9 8 5 4 3 2 1 0
Fault IGN 0 0
Coarse
page table
Coarse page table base address
Section Section base address SBZ TEX AP
Note
ARMv5TE includes optional support for Supersections, Shareable memory, and the TEX bitfield. See
Virtual memory support on page AppxH-21.
Use of the SCTLR.S and SCTLR.R bits described in Table H-6 on page AppxH-23 is deprecated. They are
implemented for use only with the legacy format translation tables, and their use is not supported in
VMSAv6 or VMSAv7.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxG-25
I
M
P
I
M
P
Domain SBZ 0 1
Domain
S
B
Z
C B 1 0
Reserved 1 1