ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Locked, bit [1]
Debug Registers Reference
This bit indicates the status of the OS Lock. The possible values are:
0 Lock not set.
1 Lock set. Writes to debug registers are ignored.
The OS Lock is set or cleared by writing to the DBGOSLAR, see OS Lock Access Register
(DBGOSLAR) on page C10-75.
On a debug logic reset the state of the OS Lock and the value of this bit are
IMPLEMENTATION DEFINED. If the implementation includes the recommended external
debug interface they are determined by the value of the DBGOSLOCKINIT signal:
DBGOSLOCKINIT LOW
The lock is not set, and the Locked bit is 0
DBGOSLOCKINIT HIGH
The lock is set, and the Locked bit is 1.
Lock implemented, bit [0]
This bit reads 1 if it is possible to set the OS Lock for this processor.
If this bit reads 0, OS Lock and the OS Save and Restore mechanism are not implemented
and the entire register is RAZ.
C10.6.3 OS Save and Restore Register (DBGOSSRR)
The OS Save and Restore Register, DBGOSSRR, enables the entire debug logic state of the processor to be
either saved or restored, by performing a series of reads or writes of the DBGOSSRR. The register works
in conjunction with an internal sequence counter to perform the OS Save or Restore operation.
The DBGOSSRR is:
debug register 194, at offset 0x308
a read/write register
only defined in v7 Debug
when the Security Extensions are implemented, a Common register.
Note
In a v7 Debug implementation that does not implement the OS Save and Restore mechanism, register
194 is RAZ/WI.
For more information about access permissions in an implementation that includes the OS Save and
Restore mechanism but does not provide access to the DBGOSSRR through the external debug
interface, see the Note in The OS Save and Restore mechanism on page C6-8.
In v6 Debug and v6.1 Debug, register 194 is not defined.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-77