ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Memory-mapped trace model, bits [19:16]
The CPUID Identification Scheme
Support for memory-mapped trace model. Permitted values are:
0b0000 Not supported.
0b0001 Support for ARM trace architecture, with memory-mapped access.
The ID register, register 0x079, gives more information about the
implementation. See also Trace on page C1-5.
Coprocessor trace model, bits [15:12]
Support for coprocessor-based trace model. Permitted values are:
0b0000 Not supported.
0b0001 Support for ARM trace architecture, with CP14 access.
The ID register, register 0x079, gives more information about the
implementation. See also Trace on page C1-5.
Memory-mapped debug model, A and R profiles, bits [11:8]
Support for memory-mapped debug model, for A and R profile processors. Permitted values
are:
0b0000 Not supported, or pre-ARMv6 implementation.
0b0100 Support for v7 Debug architecture, with memory-mapped access.
Values 0b0001, 0b0010, and 0b0011 are reserved.
Coprocessor Secure debug model, bits [7:4]
Support for coprocessor-based Secure debug model, for an A profile processor that includes
the Security Extensions. Permitted values are:
0b0000 Not supported.
0b0011 Support for v6.1 Debug architecture, with CP14 access.
0b0100 Support for v7 Debug architecture, with CP14 access.
Values 0b0001 and 0b0010 are reserved.
Coprocessor debug model, bits [3:0]
Support for coprocessor based debug model, for A and R profile processors. Permitted
values are:
0b0000 Not supported.
0b0010 Support for v6 Debug architecture, with CP14 access.
0b0011 Support for v6.1 Debug architecture, with CP14 access.
0b0100 Support for v7 Debug architecture, with CP14 access.
Value 0b0001 is reserved.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B5-7