ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.395 VST3 (multiple 3-element structures)
This instruction stores multiple 3-element structures to memory from three registers, with interleaving. For
more information, see Element and structure load/store instructions on page A4-27. Every element of each
register is saved. For details of the addressing mode see Advanced SIMD addressing mode on page A7-30.
Encoding T1 / A1 Advanced SIMD
VST3. , [{@}]{!}
VST3. , [{@}],
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 0 D 0 0 Rn Vd type size align Rm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd type size align Rm
if size == ‘11’ || align == ‘1’ then UNDEFINED;
case type of
when ‘0100’
inc = 1;
when ‘0101’
inc = 2;
otherwise
SEE “Related encodings”;
alignment = if align == ‘0’ then 1 else 8;
ebytes = 1 31 then UNPREDICTABLE;
Related encodings See Advanced SIMD element or structure load/store instructions on page A7-27
Assembler syntax
VST3. , [{@}] Rm = ’1111’
VST3. , [{@}]! Rm = ’1101’
VST3. , [{@}], Rm = other values
where:
See Standard assembler syntax fields on page A8-7. An ARM VST3 instruction must be
unconditional.
The data size. It must be one of:
8 encoded as size = 0b00
16 encoded as size = 0b01
32 encoded as size = 0b10.
A8-776 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B