ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
If an exception is taken in Monitor mode in Non-debug state, the SCR.NS bit is set to zero, see c1,
Secure Configuration Register (SCR) on page B3-106. This forces Secure state entry for all
exceptions. However, if an exception is taken in Monitor mode in Debug state, the SCR.NS bit is not
set to zero.
Note
Many uses of the Security Extensions can be simplified if the system is designed so that exceptions
cannot be taken in Monitor mode.
Setting bits in the Secure Configuration Register causes one or more of external aborts, IRQs and
FIQs to be handled in Monitor mode and to use the Monitor exception base address:
— setting the SCR.EA bit to 1 means external aborts are handled in Monitor mode, instead of
Abort mode
— setting the SCR.FIQ bit to 1 means FIQs are handled in Monitor mode, instead of FIQ mode
— setting the SCR.IRQ bit to 1 means IRQs are handled in Monitor mode, instead of IRQ mode.
For more information see:
— Control of exception handling by the Security Extensions on page B1-41
— c1, Secure Configuration Register (SCR) on page B3-106.
Setting bits in the Secure Configuration Register prevents code executing in Non-secure state from
being able to mask one or both of asynchronous aborts and FIQs:
— Setting the SCR.AW bit to 1 prevents Non-secure setting of CPSR.A to 1.
— Setting the SCR.FW bit to 1 prevents Non-secure setting of CPSR.F to 1. For details of how
this setting interacts with NMFIs see Non-maskable fast interrupts on page B1-18.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B1-29