ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.167 SMLAD
Signed Multiply Accumulate Dual performs two signed 16 x 16-bit multiplications. It adds the products to
a 32-bit accumulate operand.
Optionally, you can exchange the halfwords of the second operand before performing the arithmetic. This
produces top × bottom and bottom × top multiplication.
This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the
multiplications.
Encoding T1 ARMv6T2, ARMv7
SMLAD{X} ,,,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 1 1 0 0 1 0 Rn Ra Rd 0 0 0 M Rm
if Ra == ‘1111’ then SEE SMUAD;
d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); a = UInt(Ra);
m_swap = (M == ‘1’);
if BadReg(d) || BadReg(n) || BadReg(m) || a == 13 then UNPREDICTABLE;
Encoding A1 ARMv6*, ARMv7
SMLAD{X} ,,,
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 1 1 1 0 0 0 0 Rd Ra Rm 0 0 M 1 Rn
if Ra == ‘1111’ then SEE SMUAD;
d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); a = UInt(Ra);
m_swap = (M == ‘1’);
if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
A8-332 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B