ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Common VFP Subarchitecture Specification
B.6 Subarchitecture additions to the VFP system registers
The Common VFP subarchitecture requires additions to the VFP system register implementation:
extra fields are defined in the FPEXC, see Additions to the Floating-Point Exception Register
(FPEXC)
additional VFP registers might be defined, see The Floating-Point Instruction Registers, FPINST and
FPINST2 on page AppxB-20.
Also, the Subarchitecture field of the FPSID must identify the Common VFP subarchitecture version, see
Floating-point System ID Register (FPSID) on page B5-34.
For more information about the VFP register implementation for the Common VFP subarchitecture see:
Detecting which VFP Common subarchitecture registers are implemented on page AppxB-22
Accessing the VFP Common subarchitecture registers on page AppxB-22.
B.6.1 Additions to the Floating-Point Exception Register (FPEXC)
See The Floating-Point Exception Register (FPEXC) on page B1-68 for the architectural definition of the
FPEXC, including its purpose and accessibility.
The format of the FPEXC when version 3 of the Common VFP subarchitecture is implemented
is:
31 30 29 28 27 26 25 21 20
11 10 8 7 6 5 4 3 2 1
EX EN
UNK/SBZP IMPLEMENTATION DEFINED VECITR
DEX
FP2V
VV
TFV
IMPLEMENTATION DEFINED
EX, bit [31] See The Floating-Point Exception Register (FPEXC) on page B1-68 for the definition of
this bit.
On an implementation that does not require asynchronous exception handling this bit is
RAZ/WI. In this case the FPINST and FPINST2 registers are not implemented.
For details of how, in Common VFP subarchitecture v1, the meaning of the EX bit changes
when the FPSR.IEX bit is set to 1, see Subarchitecture v1 exception handling when
FPSCR.IXE == 1 on page AppxB-23.
EN, bit [30] See The Floating-Point Exception Register (FPEXC) on page B1-68 for the definition of
this bit.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxB-15
IDF
IXF
UFF
OFF
DZF
IOF
0