ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Register Index
Register In a Description, see
Floating-point Instruction The Floating-Point Instruction Registers, FPINST and FPINST2 on
page AppxB-20
Floating-point System ID Floating-point System ID Register (FPSID) on page B5-34
Format D Data Cache Lockdown,
pre-ARMv7
c9, Format D Data or unified Cache Lockdown Register, DCLR2 on
page AppxH-58
FPEXC The Floating-Point Exception Register (FPEXC) on page B1-68
FPINST The Floating-Point Instruction Registers, FPINST and FPINST2 on
page AppxB-20
FPINST2 The Floating-Point Instruction Registers, FPINST and FPINST2 on
page AppxB-20
FPSCR Floating-point Status and Control Register (FPSCR) on page A2-28
FPSID Floating-point System ID Register (FPSID) on page B5-34
FSR See Fault Status
Host to Target Data Transfer Host to Target Data Transfer Register (DBGDTRRX) on page C10-40
IAPR, pre-ARMv6 c5, Memory Region Access Permissions Registers (DAPR and IAPR) on
page AppxH-45
ICIALLU PMSA CP15 c7, Cache and branch predictor maintenance functions on
page B4-68
VMSA CP15 c7, Cache and branch predictor maintenance functions on
page B3-126
ICIALLUIS PMSA CP15 c7, Cache and branch predictor maintenance functions on
page B4-68
VMSA CP15 c7, Cache and branch predictor maintenance functions on
page B3-126
ICIMVAU PMSA CP15 c7, Cache and branch predictor maintenance functions on
page B4-68
VMSA CP15 c7, Cache and branch predictor maintenance functions on
page B3-126
ICLR, pre-ARMv7 c9, cache lockdown support on page AppxH-52
Table K-1 Register index (continued)
AppxK-12 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B