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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Common Memory System <strong>Architecture</strong> Features<br />

B2.2.5 The interaction of cache lockdown with cache maintenance<br />

The interaction of cache lockdown <strong>and</strong> cache maintenance operations is IMPLEMENTATION DEFINED.<br />

However, an architecturally-defined cache maintenance operation on a locked cache line must comply with<br />

the following general rules:<br />

The effect of these operations on locked cache entries is IMPLEMENTATION DEFINED:<br />

— cache clean by set/way<br />

— cache invalidate by set/way<br />

— cache clean <strong>and</strong> invalidate by set/way<br />

— instruction cache invalidate all.<br />

However, one of the following approaches must be adopted in all these cases:<br />

1. If the operation specified an invalidation a locked entry is not invalidated from the cache. If the<br />

operation specified a clean it is IMPLEMENTATION DEFINED whether locked entries are cleaned.<br />

2. If an entry is locked down, or could be locked down, an IMPLEMENTATION DEFINED Data Abort<br />

exception is generated, using the fault status code defined for this purpose in CP15 c5, see<br />

either:<br />

Fault Status <strong>and</strong> Fault Address registers in a VMSA implementation on page B3-48<br />

Fault Status <strong>and</strong> Fault Address registers in a PMSA implementation on page B4-18.<br />

This permits a typical usage model for cache invalidate routines to operate on a large range of<br />

addresses by performing the required operation on the entire cache, without having to consider<br />

whether any cache entries are locked. The operation performed is either an invalidate, or a clean <strong>and</strong><br />

invalidate.<br />

The effect of these operations is IMPLEMENTATION DEFINED:<br />

— cache clean by MVA<br />

— cache invalidate by MVA<br />

— cache clean <strong>and</strong> invalidate by MVA.<br />

However, one of the following approaches must be adopted in all these cases:<br />

1. If the operation specified an invalidation a locked entry is invalidated from the cache. For the<br />

clean <strong>and</strong> invalidate operation, the entry must be cleaned before it is invalidated.<br />

2. If the operation specified an invalidation a locked entry is not invalidated from the cache. If the<br />

operation specified a clean it is IMPLEMENTATION DEFINED whether locked entries are cleaned<br />

3. If an entry is locked down, or could be locked down, an IMPLEMENTATION DEFINED Data Abort<br />

exception is generated, using the fault status code defined for this purpose in CP15 c5, see<br />

either:<br />

Fault Status <strong>and</strong> Fault Address registers in a VMSA implementation on page B3-48<br />

Fault Status <strong>and</strong> Fault Address registers in a PMSA implementation on page B4-18.<br />

An implementation that uses the abort mechanisms for entries that could be locked must:<br />

document IMPLEMENTATION DEFINED code sequences that then perform the required operation on<br />

entries that are not locked down<br />

B2-18 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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