ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
B3.9 Fault Status and Fault Address registers in a VMSA implementation
This section describes the Fault Status and Fault Address registers, and how they report information about
VMSA aborts. It contains the following subsections:
About the Fault Status and Fault Address registers
Data Abort exceptions on page B3-49
Prefetch Abort exceptions on page B3-49
Fault Status Register encodings for the VMSA on page B3-50
Distinguishing read and write accesses on Data Abort exceptions on page B3-52
Provision for classification of external aborts on page B3-52
The Domain field in the DFSR on page B3-52
Auxiliary Fault Status Registers on page B3-53.
Also, these registers are used to report information about debug exceptions. For details see Effects of debug
exceptions on CP15 registers and the DBGWFAR on page C4-4.
B3.9.1 About the Fault Status and Fault Address registers
VMSAv7 provides four registers for reporting fault address and status information:
The Data Fault Status Register, see c5, Data Fault Status Register (DFSR) on page B3-121. The
DFSR is updated on taking a Data Abort exception.
The Instruction Fault Status Register, see c5, Instruction Fault Status Register (IFSR) on
page B3-122. The IFSR is updated on taking a Prefetch Abort exception.
The Data Fault Address Register, see c6, Data Fault Address Register (DFAR) on page B3-124. In
some cases, on taking a synchronous Data Abort exception the DFAR is updated with the faulting
address. See Terminology for describing exceptions on page B1-4 for a description of synchronous
exceptions.
The Instruction Fault Address Register, see c6, Instruction Fault Address Register (IFAR) on
page B3-125. The IFAR is updated with the faulting address on taking a Prefetch Abort exception.
In addition, the architecture provides encodings for two IMPLEMENTATION DEFINED Auxiliary Fault Status
Registers, see Auxiliary Fault Status Registers on page B3-53.
Note
On a Data Abort exception that is generated by an instruction cache maintenance operation, the IFSR
is also updated.
Before ARMv7, the Data Fault Address Register (DFAR) was called the Fault Address Register
(FAR).
B3-48 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B