ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

B3.12.23 CP15 c2 and c3, Memory protection and control registers
Virtual Memory System Architecture (VMSA)
On an ARMv7-A implementation, the CP15 c2 and c3 registers are used for memory protection and control.
Figure B3-14 shows these registers.
CRn opc1 CRm opc2
c2 0 c0
0
TTBR0, Translation Table Base Register 0
1 TTBR1, Translation Table Base Register 1
2
TTBCR, Translation Table Base Control Register
c3 0 c0 0
DACR, Domain Access Control Register
Read-only Read/Write
Write-only
Figure B3-14 CP15 c2 and c3 registers
CP15 c2 and c3 register encodings not shown in Figure B3-14 are UNPREDICTABLE, see Unallocated CP15
encodings on page B3-69.
B3.12.24 CP15 c2, Translation table support registers
When the VMSA is implemented, three translation table support registers are implemented in CP15 c2.
Table B3-28 summarizes these registers.
Register name Description
The description of the TTBCR describes the use of this set of registers, see c2, Translation Table Base
Control Register (TTBCR) on page B3-117.
c2, Translation Table Base Register 0 (TTBR0)
Table B3-28 VMSA translation table support registers
Translation Table Base 0 c2, Translation Table Base Register 0 (TTBR0)
Translation Table Base 1 c2, Translation Table Base Register 1 (TTBR1) on page B3-116
Translation Table Base Control c2, Translation Table Base Control Register (TTBCR) on page B3-117
The Translation Table Base Register 0, TTBR0, holds the base address of translation table 0, and
information about the memory it occupies.
The TTBR0 register:
is a 32-bit read/write register
is accessible only in privileged modes
when the Security Extensions are implemented:
— is a Banked register.
— has write access to the Secure copy of the register disabled when the CP15SDISABLE signal
is asserted HIGH.
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