ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.48 HB, HBL, HBLP, HBP
A8.6.49 ISB
These are ThumbEE instructions. For details see HB, HBL on page A9-16, HBLP on page A9-17, and HBP
on page A9-18.
Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following
the ISB are fetched from cache or memory, after the instruction has been completed. It ensures that the effects
of context altering operations, such as changing the ASID, or completed TLB maintenance operations, or
branch predictor maintenance operations, as well as all changes to the CP15 registers, executed before the
ISB instruction are visible to the instructions fetched after the ISB.
In addition, any branches that appear in program order after the ISB instruction are written into the branch
prediction logic with the context that is visible after the ISB instruction. This is needed to ensure correct
execution of the instruction stream.
Encoding T1 ARMv7
ISB #
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 0 1 1 (1)(1)(1) (1) 1 0 (0) 0 (1)(1)(1)(1) 0 1 1 0 option
// No additional decoding required
Encoding A1 ARMv7
ISB #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 1 0 1 1 1 (1)(1)(1)(1)(1)(1)(1)(1)(0)(0)(0)(0) 0 1 1 0 option
// No additional decoding required
A8-102 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B