ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Register In a Description, see
Control PMSA c1, System Control Register (SCTLR) on page B4-45
VMSA c1, System Control Register (SCTLR) on page B3-96
Register Index
Coprocessor Access Control PMSA c1, Coprocessor Access Control Register (CPACR) on page B4-51
VMSA c1, Coprocessor Access Control Register (CPACR) on page B3-104
Count Enable Clear c9, Count Enable Clear Register (PMCNTENCLR) on page C10-109
Count Enable Set c9, Count Enable Set Register (PMCNTENSET) on page C10-108
CPACR PMSA c1, Coprocessor Access Control Register (CPACR) on page B4-51
VMSA c1, Coprocessor Access Control Register (CPACR) on page B3-104
CPSR The Current Program Status Register (CPSR) on page B1-14
CSSELR PMSA c0, Cache Size Selection Register (CSSELR) on page B4-43
VMSA c0, Cache Size Selection Register (CSSELR) on page B3-95
CTR PMSA c0, Cache Type Register (CTR) on page B4-34
VMSA c0, Cache Type Register (CTR) on page B3-83
Cycle Count c9, Cycle Count Register (PMCCNTR) on page C10-114
D0 - D31 Advanced SIMD and VFP extension registers on page A2-21
DACR VMSA c3, Domain Access Control Register (DACR) on page B3-119
DAPR, pre-ARMv6 c5, Memory Region Access Permissions Registers (DAPR and IAPR) on
page AppxH-45
Data Fault Address PMSA c6, Data Fault Address Register (DFAR) on page B4-57
VMSA c6, Data Fault Address Register (DFAR) on page B3-124
Data Fault Status PMSA c5, Data Fault Status Register (DFSR) on page B4-55
Data Memory Region Access
Permissions, pre-ARMv6
Data Memory Region Bufferability,
pre-ARMv6
Table K-1 Register index (continued)
VMSA c5, Data Fault Status Register (DFSR) on page B3-121
c5, Memory Region Access Permissions Registers (DAPR and IAPR) on
page AppxH-45
c3, Memory Region Bufferability Register (DBR) on page AppxH-44
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxK-5