ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

B3.12.7 c0, Main ID Register (MIDR)
Virtual Memory System Architecture (VMSA)
The Main ID Register, MIDR, provides identification information for the processor, including an
implementer code for the device and a device ID number.
The MIDR is:
a 32-bit read-only register
accessible only in privileged modes
when the Security Extensions are implemented, a Common register.
Some fields of the MIDR are IMPLEMENTATION DEFINED. For details of the values of these fields for a
particular ARMv7 implementation, and any implementation-specific significance of these values, see the
product documentation.
The format of the MIDR is:
31 24 23 20 19 16 15 4 3 0
Implementer Variant Architecture Primary part number Revision
Implementer, bits [31:24]
Variant, bits [23:20]
The Implementer code. Table B3-20 shows the permitted values for this field:
Bits [31:24] ASCII character Implementer
0x41 A ARM Limited
All other values are reserved by ARM and must not be used.
Table B3-20 Implementer codes
0x44 D Digital Equipment Corporation
0x4D M Motorola, Freescale Semiconductor Inc.
0x51 Q QUALCOMM Inc.
0x56 V Marvell Semiconductor Inc.
0x69 i Intel Corporation
An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish
between different product variants, or major revisions of a product.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-81