ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Register Interfaces
the external debug interface knows when the core power domain is powered down, and can
communicate this information to the external debugger.
For details of these signals see DBGNOPWRDWN on page AppxA-9 and DBGPWRDUP on
page AppxA-10.
If the core power domain is not being powered down at the same time as the debug power domain then the
authentication signal DBGEN must be pulled LOW before power is removed from the debug power domain.
The behavior of the debug logic, and in particular the generation of debug events, is UNPREDICTABLE when
the debug power domain is not powered if DBGEN is not LOW. Pulling DBGEN LOW ensures that debug
events are ignored by the processor. For more information, see Changing the authentication signals on
page AppxA-4.
Reads and writes of debug registers when the debug logic is powered down are UNPREDICTABLE.
The performance monitors must be implemented in the core power domain, and must continue to operate
when debug power is removed.
The rest of this part of this manual assumes that two power domains are implemented as described in this
section, and that therefore the implementation supports debug over power-down. Features that are not
required for an ARMv7 implementation with a single power domain are identified as SinglePower, with a
description of the differences in behavior. A SinglePower implementation cannot support debug over
power-down.
C6.2.3 The OS Save and Restore mechanism
The OS Save and Restore mechanism enables an operating system to save the debug registers before
power-down and restore them when power is restored. This extends the support for debug over power-down,
and permits debug tools to work at a higher level of abstraction when there are no power-down events.
In v7 Debug:
If an implementation supports debug over power-down, then it must implement the OS Save and
Restore mechanism.
On a SinglePower implementation, and on any other implementation that does not support debug over
power-down, it is IMPLEMENTATION DEFINED whether the OS Save and Restore mechanism is
implemented.
If the OS Save and Restore mechanism is not implemented, the DBGOSLSR must be implemented
as RAZ, and the other OS Save and Restore mechanism register encodings must be RAZ/WI.
In v6 Debug and v6.1 Debug, these registers are not defined.
Two of the requirements for an implementation that supports debug over power-down are:
An operating system must be able to save and restore the much of the debug logic state over a
power-down. This requirement is met by the OS Save and Restore mechanism.
A debugger must be able to detect that a processor has powered-down. For more information, see
Permissions in relation to power-down on page C6-28.
C6-8 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B