ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Advanced SIMD and VFP Instruction Encoding
A7.6 Extension register load/store instructions
If T == 1 in the Thumb encoding or cond == 0b1111 in the ARM encoding, the instruction is UNDEFINED.
Otherwise, the allocation of encodings in this space is shown in Table A7-19. Other encodings in this space
are UNDEFINED.
These instructions are LDC and STC instructions for coprocessors 10 and 11.
Thumb encoding
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 T 1 1 0 Opcode Rn 1 0 1
ARM encoding
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 1 0 Opcode Rn 1 0 1
Table A7-19 Extension register load/store instructions
Opcode Rn Instruction See
0010x - - 64-bit transfers between ARM
core and extension registers on
page A7-32
01x00 - Vector Store Multiple (Increment After, no writeback) VSTM on page A8-784
01x10 - Vector Store Multiple (Increment After, writeback) VSTM on page A8-784
1xx00 - Vector Store Register VSTR on page A8-786
10x10 not 1101 Vector Store Multiple (Decrement Before, writeback) VSTM on page A8-784
1101 Vector Push Registers VPUSH on page A8-696
01x01 - Vector Load Multiple (Increment After, no writeback) VLDM on page A8-626
01x11 not 1101 Vector Load Multiple (Increment After, writeback) VLDM on page A8-626
1101 Vector Pop Registers VPOP on page A8-694
1xx01 - Vector Load Register VLDR on page A8-628
10x11 - Vector Load Multiple (Decrement Before, writeback) VLDM on page A8-626
A7-26 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B