ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
B3.12 CP15 registers for a VMSA implementation
This section gives a full description of the registers implemented in the CP15 System Control Coprocessor
in an ARMv7 implementation that includes the VMSA memory system. Therefore, this is the description
of the CP15 registers for an ARMv7-A implementation.
Some of the registers described in this section are also included in an ARMv7 implementation with a PMSA.
The section CP15 registers for a PMSA implementation on page B4-22 also includes descriptions of these
registers.
See Coprocessors and system control on page B1-62 for general information about the System Control
Coprocessor, CP15 and the register access instructions MRC and MCR.
Information in this section is organized as follows:
general information is given in:
— Organization of the CP15 registers in a VMSA implementation
— General behavior of CP15 registers on page B3-68
— Effect of the Security Extensions on the CP15 registers on page B3-71
— Changes to CP15 registers and the memory order model on page B3-77
— Meaning of fixed bit values in register diagrams on page B3-78.
this is followed by, for each of the primary CP15 registers c0 to c15:
— a general description of the organization of the primary CP15 register
— detailed descriptions of all the registers in that primary register.
Note
The detailed descriptions of the registers that implement the processor identification scheme, CPUID,
are given in Chapter B5 The CPUID Identification Scheme, and not in this section.
Table B3-14 on page B3-66 lists all of the CP15 registers in a VMSA implementation, and is an index to the
detailed description of each register.
B3.12.1 Organization of the CP15 registers in a VMSA implementation
Figure B3-10 on page B3-65 summarizes the ARMv7 CP15 registers when the VMSA is implemented.
Table B3-14 on page B3-66 lists all of these registers.
Note
ARMv7 introduces significant changes to the memory system registers, especially in relation to caches. For
details of:
the CP15 register implementation in VMSAv6, see Organization of CP15 registers for an ARMv6
VMSA implementation on page AppxG-29
how the ARMv7 registers must be used to discover what caches can be accessed by the processor, see
Identifying the cache resources in ARMv7 on page B2-4.
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