ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Note
ARM recommends that an implementation that supports sample-based profiling:
implements both DBGPCSR and DBGCIDSR
implements DBGPCSR as register 40
Sample-based Profiling
also implements DBGPCSR as register 33, for backwards compatibility with implementations that
implement it only as register 33.
C8.1.2 Reads of the Program Counter sampling registers
A read of the DBGPCSR:
Normally:
— returns the address of an instruction recently executed by the processor
— sets the DBGCIDSR, if implemented, to the current value of the CONTEXTIDR.
For more information about the CONTEXTIDR, see:
— c13, Context ID Register (CONTEXTIDR) on page B3-153, for a VMSA implementation
— c13, Context ID Register (CONTEXTIDR) on page B4-76, for a PMSA implementation.
Alternatively, when any of the following is true, returns 0xFFFFFFFF and sets the DBGCIDSR, if
implemented, to an UNKNOWN value:
— non-invasive debug is disabled
— the processor is in a mode or state where non-invasive debug is not permitted
— the processor is in Debug state.
If the DBGCIDSR is implemented, reading it returns the last value to which it was set.
Note
The ARM architecture does not define recently executed. The delay between an instruction being executed
by the processor and its address appearing in the DBGPCSR is not defined. For example, if a piece of code
reads the DBGPCSR of the processor it is running on, there is no guaranteed relationship between the
program counter for that piece of code and the value read. The DBGPCSR is intended only for use by an
external agent to provide statistical information for code profiling.
The value in the DBGPCSR always references a committed instruction. An implementation must not sample
values that reference instructions that are fetched but not committed for execution.
If DBGPCSR is implemented, it must be possible to sample references to branch targets. It is
IMPLEMENTATION DEFINED whether references to other instructions can be sampled. ARM recommends that
a reference to any instruction can be sampled.
The branch target for a conditional branch instruction that fails its condition code check is the instruction
that follows the conditional branch instruction. The branch target for an exception is the exception vector
address.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C8-3