ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

C1.2 About the ARM Debug architecture
ARM processors implement two types of debug support:
Introduction to the ARM Debug Architecture
Invasive debug All debug features that permit modification of processor state. For more
information, see Invasive debug.
Non-invasive debug All debug features that permit data and program flow observation, especially trace
support. For more information, see Non-invasive debug on page C1-5.
The following sections introduce invasive and non-invasive debug. Summary of the ARM debug component
descriptions on page C1-7 gives a quick reference summary of the rest of this part of this manual.
C1.2.1 Invasive debug
The invasive debug component of the ARM Debug architecture is intended primarily for run-control
debugging.
Note
In this part of this manual, invasive debug is often referred to simply as debug. For example, debug events,
debug exceptions, and Debug state are all part of the invasive debug implementation.
The programmers’ model can be used to manage and control debug events. Watchpoints and breakpoints are
two examples of debug events. Debug events are described in Chapter C3 Debug Events.
You can configure the processor through the DBGDSCR into one of two debug-modes:
Monitor debug-mode
In Monitor debug-mode, a debug event causes a debug exception to occur:
a debug exception that relates to instruction execution generates a Prefetch Abort
exception
a debug exception that relates to a data access generates a Data Abort exception.
Debug exceptions are described in Chapter C4 Debug Exceptions.
Halting debug-mode
In Halting debug-mode, a debug event causes the processor to enter a special Debug state.
When the processor is in Debug state, the processor ceases to execute instructions from the
program counter location, but is instead controlled through the external debug interface, in
particular the Instruction Transfer Register (DBGITR). This enables an external agent, such
as a debugger, to interrogate processor context, and control all subsequent instruction
execution. Because the processor is stopped, it ignores the system and cannot service
interrupts.
Debug state is described in Chapter C5 Debug State.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C1-3