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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Instruction Details<br />

A8.6.363 VQRDMULH<br />

Vector Saturating Rounding Doubling Multiply Returning High Half multiplies corresponding elements in<br />

two vectors, doubles the results, <strong>and</strong> places the most significant half of the final results in the destination<br />

vector. The results are rounded (for truncated results see VQDMULH on page A8-704).<br />

The second oper<strong>and</strong> can be a scalar instead of a vector. For more information about scalars see Advanced<br />

SIMD scalars on page A7-9.<br />

If any of the results overflow, they are saturated. The cumulative saturation flag, QC, is set if saturation<br />

occurs. For details see Pseudocode details of saturation on page A2-9.<br />

Encoding T1 / A1 Advanced SIMD<br />

VQRDMULH. ,,<br />

VQRDMULH. ,,<br />

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

1 1 1 1 1 1 1 1 0 D size Vn Vd 1 0 1 1 N Q M 0 Vm<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

1 1 1 1 0 0 1 1 0 D size Vn Vd 1 0 1 1 N Q M 0 Vm<br />

if Q == ‘1’ && (Vd == ‘1’ || Vn == ‘1’ || Vm == ‘1’) then UNDEFINED;<br />

if size == ‘00’ || size == ‘11’ then UNDEFINED;<br />

scalar_form = FALSE; esize = 8

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