ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
B3.12.16 CP15 c1, System control registers
The CP15 c1 registers are used for system control. Figure B3-12 shows the CP15 c1 registers.
CRn opc1 CRm opc2
c1 0 c0 0
1
2
c1 0
1
2
Read-only Read/Write
Write-only
* Only present if the Security Extensions are implemented.
Figure B3-12 CP15 c1 registers in a VMSA implementation
CP15 c1 register encodings not shown in Figure B3-12 are UNPREDICTABLE. When the Security Extensions
are not implemented all encodings with CRm == c1 are UNPREDICTABLE. For more information, see
Unallocated CP15 encodings on page B3-69.
The following sections describe the CP15 c1 registers:
c1, System Control Register (SCTLR)
c1, Implementation defined Auxiliary Control Register (ACTLR) on page B3-103
c1, Coprocessor Access Control Register (CPACR) on page B3-104
c1, Secure Configuration Register (SCR) on page B3-106
c1, Secure Debug Enable Register (SDER) on page B3-108
c1, Non-Secure Access Control Register (NSACR) on page B3-110.
B3.12.17 c1, System Control Register (SCTLR)
The System Control Register, SCTLR, provides the top level control of the system, including its memory
system.
The SCTLR:
Is a 32-bit read/write register, with different access rights for some bits of the register.
In ARMv7, some bits in the register are read-only. These bits relate to non-configurable features of
an ARMv7 implementation, and are provided for compatibility with previous versions of the
architecture.
Is accessible only in privileged modes.
SCTLR, Control Register
ACTLR, Auxiliary Control Register, IMPLEMENTATION DEFINED
CPACR, Coprocessor Access Control Register
* SCR, Secure Configuration Register
* SDER, Secure Debug Enable Register
* NSACR, Non-secure Access Control Register
Has a defined reset value. The reset value is IMPLEMENTATION DEFINED, see Reset value of the SCTLR
on page B3-102. When the Security Extensions are implemented the defined reset value applies only
to the Secure copy of the SCTLR, and software must program the non-banked read/write bits of the
Non-secure copy of the register with the required values.
B3-96 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B