ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.379 VRSQRTS
Vector Reciprocal Square Root Step multiplies the elements of one vector by the corresponding elements of
another vector, subtracts each of the products from 3.0, divides these results by 2.0, and places the results
into the elements of the destination vector.
The operand and result elements are 32-bit floating-point numbers.
For details of the operation performed by this instruction see Reciprocal square root on page A2-61.
Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
VRSQRTS.F32 , ,
VRSQRTS.F32 , ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 1 0 D 1 sz Vn Vd 1 1 1 1 N Q M 1 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 0 0 D 1 sz Vn Vd 1 1 1 1 N Q M 1 Vm
if Q == ‘1’ && (Vd == ‘1’ || Vn == ‘1’ || Vm == ‘1’) then UNDEFINED;
if sz == ‘1’ then UNDEFINED;
esize = 32; elements = 2;
d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); regs = if Q == ‘0’ then 1 else 2;
A8-744 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B