ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
WnR, bit [11] Write not Read bit. Indicates whether the abort was caused by a write or a read access:
0 Abort caused by a read access
1 Abort caused by a write access.
FS, bits [10,3:0]
For faults on CP15 cache maintenance operations, including the VA to PA translation
operations, this bit always returns a value of 1.
Fault status bits. For the valid encodings of these bits in an ARMv7-A implementation with
a VMSA, see Table B3-12 on page B3-51.
All encodings not shown in the table are reserved.
Domain, bits [7:4]
The domain of the fault address.
From ARMv7 use of this field is deprecated, see The Domain field in the DFSR on
page B3-52.
For information about using the DFSR see Fault Status and Fault Address registers in a VMSA
implementation on page B3-48.
Accessing the DFSR
To access the DFSR you read or write the CP15 registers with set to 0, set to c5, set to
c0, and set to 0. For example:
MRC p15,0,,c5,c0,0 ; Read CP15 Data Fault Status Register
MCR p15,0,,c5,c0,0 ; Write CP15 Data Fault Status Register
c5, Instruction Fault Status Register (IFSR)
The Instruction Fault Status Register, IFSR, holds status information about the last instruction fault.
The IFSR is:
a 32-bit read/write register
accessible only in privileged modes
when the Security Extensions are implemented, a Banked register.
The format of the IFSR is:
31 13 12 11 10 9
Bits [31:13,11,9:4]
UNK/SBZP.
UNK/SBZP
ExT
FS[4]
B3-122 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B
(0)
UNK/SBZP
4 3
FS[3:0]
0