ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
C10.1 Accessing the debug registers
In this chapter:
The debug registers are numbered sequentially from 0 to 1023.
The register offsets refer to the offsets in the v7 Debug memory-mapped or external debug interface.
The locations of these registers in the ARMv6 external debug interface might differ.
There is a standard mapping from debug register number to coprocessor instructions in the Extended CP14
interface, see Extended CP14 interface on page C6-33. The register numbers and offsets for the DBGDSCR,
DBGDTRRX, and DBGDTRTX Registers apply only to the external view of that register. For more
information, see Internal and external views of the DBGDSCR and the DCC registers on page C6-21.
Note
The recommended v7 Debug external debug interface is described in ARM Debug Interface v5
Architecture Specification.
Contact ARM if you require details of the ARMv6 recommended external debug interface.
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