ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

System Instructions
Assembler syntax
VMRS ,
where:
See Standard assembler syntax fields on page A8-7.
The destination ARM core register. This register can be R0-R14.
Is one of:
If is FPSCR, it is also permitted to be APSR_nzcv, encoded as Rt = ’1111’. This
instruction transfers the FPSCR N, Z, C, and V flags to the APSR N, Z, C, and V flags.
FPSID reg = ’0000’
FPSCR reg = ’0001’
MVFR1 reg = ’0110’
MVFR0 reg = ’0111’
FPEXC reg = ’1000’.
If the Common VFP subarchitecture is implemented, see Subarchitecture additions to the
VFP system registers on page AppxB-15 for additional values of .
The pre-UAL instruction FMSTAT is equivalent to VMRS APSR_nzcv, FPSCR.
Operation
if ConditionPassed() then
EncodingSpecificOperations();
if reg == ‘0001’ then // FPSCR
CheckVFPEnabled(TRUE); SerializeVFP(); VFPExcBarrier();
if t == 15 then
APSR.N = FPSCR.N; APSR.Z = FPSCR.Z; APSR.C = FPSCR.C; APSR.V = FPSCR.V;
else
R[t] = FPSCR;
else // Non-FPSCR registers are privileged-only and not affected by FPEXC.EN
CheckVFPEnabled(FALSE);
if !CurrentModeIsPrivileged() then UNDEFINED;
case reg of
when ‘0000’ SerializeVFP(); R[t] = FPSID;
// ‘0001’ already dealt with above
when ‘001x’ UNPREDICTABLE;
when ‘010x’ UNPREDICTABLE;
when ‘0110’ SerializeVFP(); R[t] = MVFR1;
when ‘0111’ SerializeVFP(); R[t] = MVFR0;
when ‘1000’ SerializeVFP(); R[t] = FPEXC;
otherwise SUBARCHITECTURE_DEFINED register access;
Exceptions
Undefined Instruction.
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