ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
B3.9.4 Fault Status Register encodings for the VMSA
IFSR
[10,3:0] a
01100
01110
11100
11110
00101
00111
00011 b
00110
01001
01011
01101
01111
For the fault status encodings for a VMSA implementation see:
Table B3-11 for the Instruction Fault Status Register (IFSR) encodings
Table B3-12 on page B3-51 for the Data Fault Status Register (DFSR) encodings.
Note
In previous ARM documentation, the terms precise and imprecise were used instead of synchronous and
asynchronous. For details of the more exact terminology introduced in this manual see Terminology for
describing exceptions on page B1-4.
Source IFAR Notes
Translation table walk
synchronous external abort
Translation table walk
synchronous parity error
Translation fault
Access Flag fault
Domain fault
Permission fault
1st level
2nd level
1st level
2nd level
Section
Page
Section
Page
Section
Page
Section
Page
Table B3-11 VMSAv7 IFSR encodings
B3-50 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B
Valid
Valid
Valid
Valid
Valid
Valid
-
-
MMU fault
MMU fault
MMU fault
MMU fault
00010 Debug event UNKNOWN See Software debug events on
page C3-5
01000 Synchronous external abort Valid -
10100 IMPLEMENTATION DEFINED Valid Lockdown
11010 IMPLEMENTATION DEFINED Valid Coprocessor abort
11001 Memory access synchronous parity error Valid -
a. All IFSR[10,3:0] values not listed in this table are reserved.
b. Previously, this encoding was a deprecated encoding for Alignment fault. The extensive changes in the memory model
in ARMv7 and VMSAv7 mean there should be no possibility of confusing these two uses.