ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

System Instructions
The operation. is one of ADC, ADD, AND, BIC, EOR, ORR, RSB, RSC, SBC, and SUB. Use of all
of these operations except SUB is deprecated.
The operation. is MOV or MVN. Use of MVN is deprecated.
The first operand register. Use of any register except LR is deprecated.
The immediate constant. For encoding T1, is in the range 0-255. See Modified
immediate constants in ARM instructions on page A5-9 for the range of available values in
encoding A1.
The optionally shifted second or only operand register. Use of any register except LR is
deprecated.
The shift to apply to the value read from . If absent, no shift is applied. The shifts and
how they are encoded are described in Shifts applied to a register on page A8-10. Use of
is deprecated.
The value of the operation or is encoded in the opcode field of the instruction. For the opcode
values for different operations see Operation on page B6-6.
In Thumb code, MOVS PC,LR is a pseudo-instruction for SUBS PC,LR,#0.
The pre-UAL syntax S is equivalent to S. The pre-UAL syntax S is equivalent
to S.
Operation
if ConditionPassed() then
EncodingSpecificOperations();
if CurrentInstrSet() == InstrSet_ThumbEE then
UNPREDICTABLE;
operand2 = if register_form then Shift(R[m], shift_t, shift_n, APSR.C) else imm32;
case opcode of
when ‘0000’ result = R[n] AND operand2; // AND
when ‘0001’ result = R[n] EOR operand2; // EOR
when ‘0010’ (result, -, -) = AddWithCarry(R[n], NOT(operand2), ‘1’); // SUB
when ‘0011’ (result, -, -) = AddWithCarry(NOT(R[n]), operand2, ‘1’); // RSB
when ‘0100’ (result, -, -) = AddWithCarry(R[n], operand2, ‘0’); // ADD
when ‘0101’ (result, -, -) = AddWithCarry(R[n], operand2, APSR.c); // ADC
when ‘0110’ (result, -, -) = AddWithCarry(R[n], NOT(operand2), APSR.C); // SBC
when ‘0111’ (result, -, -) = AddWithCarry(NOT(R[n]), operand2, APSR.C); // RSC
when ‘1100’ result = R[n] OR operand2; // ORR
when ‘1101’ result = operand2; // MOV
when ‘1110’ result = R[n] AND NOT(operand2); // BIC
when ‘1111’ result = NOT(operand2); // MVN
CPSRWriteByInstr(SPSR[], ‘1111’, TRUE);
BranchWritePC(result);
Exceptions
None.
B6-26 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B