ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

B.7 Version 1 of the Common VFP subarchitecture
Common VFP Subarchitecture Specification
Version 1 of the Common VFP subarchitecture has special behavior when the FPSCR.IXE bit is set to 1.
The Common VFP subarchitecture version can be identified by checking FPSID bits [22:16]. This field is
0b0000001 for version 1. In version 1 of the Common VFP subarchitecture the FPEXC.DEX bit is RAZ/WI.
B.7.1 Subarchitecture v1 exception handling when FPSCR.IXE == 1
In version 1 of the Common VFP subarchitecture, the mechanism for bouncing instructions changes when
the FPSCR.IXE bit, the Inexact exception enable bit, is set to 1.
When FPSCR.IXE is set to 1, the FPEXC.EX bit signals a synchronous exception, in the same way as the
FPEXC.DEX bit. In this case:
the exceptional instruction is the instruction that caused the Undefined Instruction exception
the FPINST Register and the FPEXC.VECITR field are not valid.
When FPSCR.IXE is 0 the FPEXC.EX bit signals an asynchronous exception, as for later versions of the
subarchitecture.
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