ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Accessing the ACTLR
Protected Memory System Architecture (PMSA)
To access the ACTLR you read or write the CP15 registers with set to 0, set to c1, set to
c0, and set to 1. For example:
MRC p15,0,,c1,c0,1 ; Read CP15 Auxiliary Control Register
MCR p15,0,,c1,c0,1 ; Write CP15 Auxiliary Control Register
B4.6.18 c1, Coprocessor Access Control Register (CPACR)
The Coprocessor Access Control Register, CPACR, controls access to all coprocessors other than CP14 and
CP15. It also enables software to check for the presence of coprocessors CP0 to CP13.
The CPACR:
is a 32-bit read/write register
is accessible only in privileged modes.
has a defined reset value of 0.
The format of the CPACR is:
31 30 29 28 27
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASEDIS, bit[31]
(0) (0) cp13 cp12 cp11 cp10 cp9 cp8 cp7 cp6 cp5 cp4 cp3 cp2 cp1 cp0
D32DIS
ASEDIS
Disable Advanced SIMD functionality:
0 This bit does not cause any instructions to be UNDEFINED.
1 All instruction encodings identified in the Alphabetical list of instructions on
page A8-14 as being part of Advanced SIMD, but that are not VFPv3
instructions, are UNDEFINED.
On an implementation that:
Implements VFP and does not implement Advanced SIMD, this bit is RAO/WI.
Does not implement VFP or Advanced SIMD, this bit is UNK/SBZP.
Implements both VFP and Advanced SIMD, it is IMPLEMENTATION DEFINED whether
this bit is supported. If it is not supported it is RAZ/WI.
This bit resets to 0 if it is supported.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B4-51