ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
Table C10-18 Interaction of CP15 Cache Behavior Override Register (CBOR) and DBGDSCCR
DBGDSCCR setting CBOR setting Debug state Behavior
nWT = 1 WT = 0 X Areas marked WB are Write-Back
nWT = X WT = 0 No Areas marked WB are Write-Back
nWT = X WT = 1 X Areas marked WB are Write-Through
nWT = 0 WT = X Yes Areas marked WB are Write-Through
nDL = 1 DL = 0 X Data or unified cache linefills are enabled
nDL = X DL = 0 No Data or unified cache linefills are enabled
nDL = X DL = 1 X Data or unified cache linefills are disabled
nDL = 0 DL = X Yes Data or unified cache linefills are disabled
nIL = 1 IL = 0 X Instruction cache linefills are enabled
nIL = X IL = 0 No Instruction cache linefills are enabled
nIL = X IL = 1 X Instruction cache linefills are disabled
nIL = 0 IL = X Yes Instruction cache linefills are disabled
A processor that does not implement Security Extensions has only WT, IL and DL settings in the CP15
Cache Behavior Override Register. Processors that implement Security Extensions can have separate
settings for, for example, NS_WT and S_WT in the CP15 Cache Behavior Override Register. For brevity
Table C10-18 does not show the full matrix of possibilities in this case. For the behavior on such a processor,
duplicate Table C10-18:
once for the Non-secure case, for example NS_WT
once for the Secure case, for example S_WT.
C10.7.2 Debug State MMU Control Register (DBGDSMCR)
The Debug State MMU Control Register, DBGDSMCR, controls TLB behavior when the processor is in
Debug state.
The DBGDSMCR is:
debug register 11, at offset 0x02C
a read/write register, with some bits that might not be implemented and therefore are RAZ/WI
required in v7 Debug
when the Security Extensions are implemented, a Common register.
C10-84 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B