ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

MRC p15,0,,c9,c12,4 UNPREDICTABLE. PMSWINC is a write-only register.
C9.8.1 Power domains and performance monitor registers reset
Performance Monitors
MCR p15,0,,c9,c12,4 c9, Software Increment Register (PMSWINC) on page C10-112.
MRC p15,0,,c9,c12,5
MCR p15,0,,c9,c12,5
MRC p15,0,,c9,c13,0
MCR p15,0,,c9,c13,0
MRC p15,0,,c9,c13,1
MCR p15,0,,c9,c13,1
MRC p15,0,,c9,c13,2
MCR p15,0,,c9,c13,2
MRC p15,0,,c9,c14,0
MCR p15,0,,c9,c14,0
MRC p15,0,,c9,c14,1
MCR p15,0,,c9,c14,1
MRC p15,0,,c9,c14,2
MCR p15,0,,c9,c14,2
Table C9-1 Recommended performance monitor registers (continued)
Instruction a Description or notes
c9, Event Counter Selection Register (PMSELR) on page C10-113.
c9, Cycle Count Register (PMCCNTR) on page C10-114.
c9, Event Type Select Register (PMXEVTYPER) on page C10-115.
c9, Event Count Register (PMXEVCNTR) on page C10-116.
c9, User Enable Register (PMUSERENR) on page C10-117.
c9, Interrupt Enable Set Register (PMINTENSET) on page C10-118.
c9, Interrupt Enable Clear Register (PMINTENCLR) on page C10-119.
a. CP15 c9 encodings with CRm == {c12-c14} not listed in the table are reserved. For details of the
behavior of accesses to these encodings see Unallocated CP15 encodings on page B3-69.
For ARMv7 implementations, ARM recommends that performance monitors are implemented as part of the
core power domain, not as part of a separate debug power domain. There is no interface to access the
performance monitor registers when the core power domain is powered down.
The performance monitor registers must be set to their reset values on a processor reset by
nSYSPORESET, nCOREPORESET or nRESET. Performance monitor registers are not changed by a
debug logic reset by PRESETDBGn.
For more information about the reset scheme recommended for a v7 Debug implementation see
Recommended reset scheme for v7 Debug on page C6-16.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C9-11