ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The CPUID Identification Scheme
0b0001 Adds support for:
the MOVT instruction
the MOV instruction encodings with zero-extended 16-bit immediates
the Thumb ADD and SUB instruction encodings with zero-extended 12-bit
immediates, and the other ADD, ADR and SUB encodings cross-referenced by
the pseudocode for those encodings.
IfThen_instrs, bits [19:16]
Indicates the supported IfThen instructions in the Thumb instruction set. Permitted values
are:
0b0000 None supported.
0b0001 Adds support for the IT instructions, and for the IT bits in the PSRs.
Extend_instrs, bits [15:12]
Indicates the supported Extend instructions. Permitted values are:
0b0000 No scalar sign-extend or zero-extend instructions are supported, where scalar
instructions means non-Advanced SIMD instructions.
0b0001 Adds support for the SXTB, SXTH, UXTB, and UXTH instructions.
0b0010 As for 0b0001, and adds support for the SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16,
UXTAB, UXTAB16, and UXTAH instructions.
Note
In addition:
the shift options on these instructions are available only if the WithShifts_instrs
attribute is 0b0011 or greater
the SXTAB16, SXTB16, UXTAB16, and UXTB16 instructions are available only if both:
— the Extend_instrs attribute is 0b0010 or greater
— the SIMD_instrs attribute is 0b0011 or greater.
Except_AR_instrs, bits [11:8]
Indicates the supported A and R profile exception-handling instructions. Permitted values
are:
0b0000 None supported.
0b0001 Adds support for the SRS and RFE instructions, and the A and R profile forms of
the CPS instruction.
Except_instrs, bits [7:4]
Indicates the supported exception-handling instructions in the ARM instruction set.
Permitted values are:
0b0000 Not supported. This indicates that the User bank and Exception return forms of
the LDM and STM instructions are not supported.
0b0001 Adds support for the LDM (exception return), LDM (user registers) and STM (user
registers) instruction versions.
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