ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
V{.} {,} , Encoded as Q = 1
V{.} {,} , Encoded as Q = 0
where:
The operation. It must be one of:
Instruction Details
BIF Bitwise Insert if False, encoded as op = 0b11. Inserts each bit from Vn
into Vd if the corresponding bit of Vm is 0, otherwise leaves the Vd bit
unchanged.
BIT Bitwise Insert if True, encoded as op = 0b10. Inserts each bit from Vn
into Vd if the corresponding bit of Vm is 1, otherwise leaves the Vd bit
unchanged.
BSL Bitwise Select, encoded as op = 0b01. Selects each bit from Vn into Vd
if the corresponding bit of Vd is 1, otherwise selects the bit from Vm.
See Standard assembler syntax fields on page A8-7. An ARM VBIF, VBIT, or VBSL
instruction must be unconditional.
An optional data type. It is ignored by assemblers, and does not affect the encoding.
, , The destination vector and the operand vectors, for a quadword operation.
, , The destination vector and the operand vectors, for a doubleword operation.
Operation
enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL};
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
case operation of
when VBitOps_VBIF D[d+r] = (D[d+r] AND D[m+r]) OR (D[n+r] AND NOT(D[m+r]);
when VBitOps_VBIT D[d+r] = (D[n+r] AND D[m+r]) OR (D[d+r] AND NOT(D[m+r]);
when VBitOps_VBSL D[d+r] = (D[n+r] AND D[d+r]) OR (D[m+r] AND NOT(D[d+r]);
Exceptions
Undefined Instruction.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-551